hello @jeloyahge.1 how did you solve the problem, am also facing the same issue after changing the IP names. Can you please help me to sort it out ?

Hey @jeloyahge.1 ,

Make sure the IP is available to the new project (i.e. in the IP path).

Maybe provide a minimal example which shows your problem.

Best,

Herbert

@hpoetzlber9

1) I made a bin to bcd converter (created the project, entered the VHDL code, synthesized it and generated the IP). Everything was OK.

2) I created some other VHDL files, synthesized them, and generated the IP's. Everything was OK.

3) Then I created a top-level project where I defined the new repository. Next I instantiated the IP created before and mapped them (PORT MAP). Everything sinthesized fine.

4) When I tried to implement this top-level project, I received the message [DRC INBB-3] Black Box Instances: Cell 'xx' of type 'xxxxxxx' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

According to Xilinx documentation, the IP can be in a different directory than the project which instantiates it. In fact, I see in the project's folder (/xxxxx_user_files/ip) some subfolders with info about the IP's instantiated (I suppose these folders were created by Vivado; I didn't created them).

What do you mean by "IP is available to the new project (in the IP path)" ?

Hi @jeloyahge.1 ,

When creating a new project, you need to add you IP directory to the IP repo path:

Hope that helps,

Regards,

Florent

@florentw

Yes, the IP's directories are already in the IP repo path (I specified the repository when I called IP catalog, then added every IP I'm going to map inside the project).

Anyway, this doesn't seem to be the issue, since Vivado is synthesizing the design OK.

Synthesis is fine, port mapping is fine, the IP's were synthesized/implemented OK, the IP route is OK. Just the Implementation is throwing the "DRC INBB-3 message error".

How is this possible?

Is there another alternative for instantiate / use those IPs?

HI @jeloyahge.1 ,

Could you share your project? I can have a look.

Regards,

Florent

@florentw

This is the project where I'm pretending to use IP:s

modules to be created as IPs:

bin_to_bcd_4b

bin_to_bcd_6b

contador_seg_min_hrs

hex_to_sseg_K

IPs created:

ip_bin_to_bcd_4b

ip_bin_to_bcd_6b

ip_contador_seg_min_hrs

ip_hex_to_sseg_K

top level project where IPs are instantiated:

reloj_s_m_h

**BEST SOLUTION**

Hi @jeloyahge.1 ,

Sorry about the delay. There is a mismatch between the name of your IPs as they have been added to the project and the name you are using to instantiate them to your project.

Basically, when you add an IP to you project, you select an name which is not necessarily the "catalog name of the IP". By default, it is not. Vivado add an index to the name. This way you could add multiple time the same IP but with different configurations.

If you modify your top level vhdl file, your issue will be solved (I have attached a corrected version).

Hope that helps,

Regards,

Florent

@florentw

It works!

When I was trying to solve this issue, once, I thought about the mismatch but never tested if this could be the problem. Your explanation sounds reasonable, but I don't remember if any part of the documentation prevents about this situation.

Thanks a lot for your invaluable time, your patience and your effort.

Hi @jeloyahge.1 ,

I don't remember if any part of the documentation prevents about this situation.

> This is more a coding issue. We cannot document every issue...