随着深度学习的高速发展, 目前智能算法的飞速更新迭代对硬件算力提出了很高的要求. 受限于摩尔定律的告竭以及冯·诺伊曼瓶颈, 传统CMOS集成无法满足硬件算力提升的迫切需求. 利用新型器件忆阻器构建神经形态计算系统可以实现存算一体, 拥有极高的并行度和超低功耗的特点, 被认为是解决传统计算机架构瓶颈的有效途径, 受到了全世界的广泛关注. 本文按照自下而上的顺序, 首先综述了主流忆阻器的器件结构、物理机理, 并比较分析了它们的性能特性. 然后, 介绍了近年来忆阻器实现人工神经元和人工突触的进展, 包括具体的电路形式和神经形态功能的模拟. 接着, 综述了无源和有源忆阻阵列的结构形式以及它们在神经形态计算中的应用, 具体包括基于神经网络的手写数字和人脸识别等. 最后总结了目前忆阻类脑计算从底层到顶层所遇到的挑战, 并对该领域后续的发展进行了展望. 忆阻器 /  人工神经元 /  人工突触 /  神经形态计算  With the rapid development of deep learning, the current rapid update and iteration of intelligent algorithms put forward high requirements for hardware computing power. Limited by the exhaustion of Moore’s law and the von Neumann bottleneck, the traditional CMOS integration cannot meet the urgent needs of hardware computing power improvement. The utilization of new device memristors to construct a neuromorphic computing system can realize the integration of storage and computing, and has the characteristics of extremely high parallelism and ultra-low power consumption. In this work, the device structure and physical mechanism of mainstream memristors are reviewed in bottom-to-top order firstly, and their performance characteristics are compared and analyzed. Then, the recent research progress of memristors to realize artificial neurons and artificial synapses is introduced, including the simulation of specific circuit forms and neuromorphic functions. Secondly, in this work, the structural forms of passive and active memristive arrays and their applications in neuromorphic computing, including neural network-based handwritten digits and face recognition, are reviewed. Lastly, the current challenges of memristive brain-like computing from the bottom to the top, are summarized and the future development of this field is also prospected. Keywords: memristor /  artificial neuron /  artificial synapse /  neuromorphic computing

Sato H, Honjo H, Watanabe T, Niwa M, Koike H, Miura S, Saito T, Inoue H, Nasuno T, Tanigawa T, Noguchi Y, Yoshiduka T, Yasuhira M, Ikeda S, Kang S Y, Kubo T, Yamashita K, Yagi Y, Tamura R, Endoh T 2018 IEEE International Electron Devices Meeting (IEDM) San Francisco, CA , December, 2018 pp27.2.1–27.2.4

Song Y J, Lee J H, Han S H, Shin H C, Lee K H, Suh K, Jeong D E, Koh G H, Oh S C, Park J H, Park S O, Bae B J, Kwon O I, Hwang K H, Seo B Y, Lee Y K, Hwang S H, Lee D S, Ji Y, Park K C, Jeong G T, Hong H S, Lee K P, Kang H K, Jung E S 2018 IEEE International Electron Devices Meeting (IEDM) San Francisco, CA , Decemeber, 2018 pp18.2.1–18.2.4

Francois T, Coignus J, Makosiej A, Giraud B, Carabasse C, Barbot J, Martin S, Castellani N, Magis T, Grampeix H, Van Duijn S, Mounet C, Chiquet P, Schroeder U, Slesazeck S, Mikolajick T, Nowak E, Bocquet M, Barrett N, Andrieu F, Grenouillet L 2021 IEEE International Electron Devices Meeting (IEDM) San Francisco, CA, USA , December 11, 2021 pp33.1.1–33.1.4

Fig. 7 . Memristor implementation of LTP: (a) Schematic illustration of the concept of using memristors as synapses between neurons; (b) memristor response to programming pulses ^{[ 101 ]} ; (c) conductance modulation performance at different initial conductance states of Pt/LiAlO _x /TiN memristor ^{[ 102 ]} ; (d) side and top profile of DW-MTJ artificial synapse; (e) update linearity and symmetry with experimental data from DW-SOT and DW-STT devices ^{[ 103 ]}

Fig. 8 . Memristor implementation of STP: (a) The corresponding current through the memristor data recorded continuously throughout the test. (b) A close-up view of the rectangular area in panel (a). (c) Dependence of the transition efficiency on stimulation rate. Current through the memristor recorded after each stimulation pulse, at different pulse interval conditions ^{[ 109 ]} . (d) The structure of ITO/PVPy–Au NPs/Al RRAM device and the HRTEM image of Au NPs. Current change between (e) two pulses and after (f) 10 pulses with different pulse intervals ^{[ 111 ]}

Fig. 9 . Memristor implementation of SRDP: (a) Schematic diagram of a biological synapse with SRDP activities ^{[ 116 ]} ; (b) WO _x based memristor response to consecutive programming pulse trains (1 V, 1 ms, blue lines) at different frequencies; (c) memristor current change as a function of the stimulation frequency after the memristor has been experienced to different levels of activities. Pulse trains consisting of five pulses (1.2 V, 1 ms) with different repetition frequencies were used to program the memristor ^{[ 118 ]}

Fig. 10 . Memristor implementation of STDP: (a) Defining spike-timing-dependent plasticity ^{[ 120 ]} ; (b) STDP realization schemes developed with TDM and pulse amplitude modulation. The pulse amplitudes for the prespike are –1.4, 1, 0.9, 0.8, 0.7, and 0.6 V, consecutively, and for the postspike, they are –1, 1.4, 1.3, 1.2, 1.1, and 1 V, consecutively. (c) Measured STDP curve of the memristors utilizing method described in panel (b) ^{[ 124 ]} . (d) Memristor weight change as a function of the relative timing between the pre- and postsynaptic pulses, Δ t = t _post – t _pre . (e) Simulation results illustrating how relative timing of the pulses affects memristor weight ^{[ 118 ]}

Fig. 12 . Neurons implemented by nonvolatile Devices: (a) Basic representation of leaky integrate-and-fire neuronal model; (b) the output current measured after excitatory input pulse with the time separated of 640 ms ^{[ 135 ]} ; (c) device schematic of PCMO RRAM; (d) SET current transient at –2.3 V showing 3 regions of operation; (e) experimental Current transient for the applied sequence of SET pulses ^{[ 136 ]}

Fig. 13 . Neurons implemented by volatile Devices: (a) Schematic illustration of the proposed neuron circuit; (b) the voltage variation across the capacitor; (c) the output neuron spike with the corresponding refractory period and integration moment ^{[ 139 ]} ; (d) the electrical circuit with two W/WO ₃ /PEDOT:PSS/Pt memristive devices; (e) spatial integration and bioinspired fire realized with the circuit; (f) temporal integration and bioinspired fire realized with the circuit ^{[ 141 ]} ; (g) schematic of neuronal circuit where the input voltage pulses originate from the signal generator; (h) the experimentally measured stochastic spike events of the CuS/GeSe based neuronal circuit under an input voltage pulse train with pulse height 2 V and duration 7.5 ms ^{[ 142 ]}

Fig. 14 . Passive memristive arrays for neuromorphic computing: (a) A schematic diagram of the typical 2D Crossbar array showing the read disturbance problem by the presence of sneak current (The thin blue line represents reading current, and the thick red line represents sneak current) ^{[ 14 ]} ; (b) an implementation of a single-layer perceptron using a 10 × 6 fragment of the memristive crossbar; (c) an example of the classification operation for a specific input pattern (stylized letter ‘z’) ^{[ 145 ]} ; (d) a schematic diagram of two 20 × 20crossbar arrays implementing a two-layer neural network ^{[ 146 ]} .

Fig. 15 . 1S1P passive memristive array for neuromorphic computing: (a) In-memory computing implemented using dense crossbar arrays of 1S1P pairs; (b) structure diagram of differential pairs; (c) the input forward propagation process of the neural network; (d) schematic diagram of neural network update ^{[ 149 ]} .

Fig. 16 . 3D passive memristive array for neuromorphic computing: (a) Equivalent circuit for two Pt/Al ₂ O ₃ /TiO _{2– x} /TiN/Pt memristors in the stacked configuration ^{[ 150 ]} ; (b) a schematic diagram showing the shared bit line structure in cross-line type 3D Crossbar array ^{[ 14 ]} ; (c) FPGA-controlled relay matrix to achieve test automation; (d) HRTEM image of the novel 3D VRRAM structure; (e) the schematic of the 3D VRRAM architecture and current flow for one convolution operation ^{[ 154 ]} .

Fig. 17 . 1T1R passive memristive array for neuromorphic computing: (a) Memristive platform for in situ learning. From left to right are: A wafer with transistor arrays, close-up of chip image, microscope image of 1T1R cell, SEM of an individual 1T1R cell, cross-sectional TEM image of the Ta/HfO ₂ /Pt memristor ^{[ 157 ]} . (b) Mapping of a one-layer neural network on the 1T1R array. (c) The micrograph of a fabricated 1024-cell-1T1R array using fully CMOS compatible fabrication process. (d) The training process flow chart. (e) The schematic of parallel read operation and how a pattern is mapped to the input ^{[ 160 ]}

Sato H, Honjo H, Watanabe T, Niwa M, Koike H, Miura S, Saito T, Inoue H, Nasuno T, Tanigawa T, Noguchi Y, Yoshiduka T, Yasuhira M, Ikeda S, Kang S Y, Kubo T, Yamashita K, Yagi Y, Tamura R, Endoh T 2018 IEEE International Electron Devices Meeting (IEDM) San Francisco, CA , December, 2018 pp27.2.1–27.2.4

Song Y J, Lee J H, Han S H, Shin H C, Lee K H, Suh K, Jeong D E, Koh G H, Oh S C, Park J H, Park S O, Bae B J, Kwon O I, Hwang K H, Seo B Y, Lee Y K, Hwang S H, Lee D S, Ji Y, Park K C, Jeong G T, Hong H S, Lee K P, Kang H K, Jung E S 2018 IEEE International Electron Devices Meeting (IEDM) San Francisco, CA , Decemeber, 2018 pp18.2.1–18.2.4

Francois T, Coignus J, Makosiej A, Giraud B, Carabasse C, Barbot J, Martin S, Castellani N, Magis T, Grampeix H, Van Duijn S, Mounet C, Chiquet P, Schroeder U, Slesazeck S, Mikolajick T, Nowak E, Bocquet M, Barrett N, Andrieu F, Grenouillet L 2021 IEEE International Electron Devices Meeting (IEDM) San Francisco, CA, USA , December 11, 2021 pp33.1.1–33.1.4

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