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Part Number: TI-JESD204-IP

Hello,

I would like to loading the reference design zc706_8b10b in Vivado. I am using Vivado 2023.2 on Ubuntu.

I am following all the steps on the doc TI204c-IP-Users-Guide at pag 53.

I imported all the design and constraint files and selected as target device the evaluation board Artix-7 AC701 . I upgrated all the IP and finally I get the error:

[DRC INBB-3] Black Box Instances: Cell 'TI_IP_inst' of type 'TI_204c_IP' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

Here is a screenshot

Hi Marco,

Kindly try the steps in Vivado 2022.x. The TI JESD IP is currently not supported in 2023.x, because Xilinx has changed its RTL encryption scheme. We are working on a new release of the JESD IP, and that will support 2023.x

Regards,

Ameet