The above case statement when put outside a process block gives a syntax
error and I am forced to put the case statement inside a process block
although I do not feel the need to do the same.
Can anyone explain what is the restriction that VHDL is imposing because
of which I am forced to define the case statement within the process
block.
Thanks in advance.
Rejoy M. wrote:
> Can anyone explain what is the restriction that VHDL is imposing because
> of which I am forced to define the case statement within the process
> block.
There are different syntax elements to do such things outside an
process. Read about "concurrent assignments" (=without process) vs.
"sequential statements" (=inside a process).
sequential coding:
1
|
process (i) begin
|
2
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case sel is
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3
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when '0' => o <= i(0);
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4
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when '1' => o <= i(1);
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5
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when others => o <= 'U';
|
6
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end case;
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7
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end process;
concurrent coding:
1
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o <= i(0) when sel='0' else
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2
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i(1) when sel='1' else
|
3
|
'U';
Rejoy M. wrote:
> Can anyone explain what is the restriction that VHDL is imposing because
> of which I am forced to define the case statement within the process
> block.
The (rather unsatisfying but correct) answer is probably: because that's
the way it is. You might as well ask why there is no concurrent "if"
statement. I would assume language designers did it this way to make it
clear to the coder that there are significant differences between
sequential and concurrent and allowed only one-liners for the latter.
Maybe the "selected concurrent signal assignment" is what you are
looking for. Although kind of backwards, it's basically the same thing:
1 | with selector select
| 2 | target <= value1 when choice1,
| 3 | target <= value2 when choice2,
| 4 | target <= default_value when others;
|
|
|
