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I understand that you can declare a string in a Verilog test bench as follows:

reg [8*14:1] string_value;  
initial 
    string_value = "Hello, World!";
I can then do things with this string, like use $display in a test bench to display it.
I haven't been successful in doing the same in a module when I flash it to my FPGA: 
reg [8*14:1] string_value;  
always @(reset) 
begin
    string_value = "Hello, World!";
    // Do stuff with string value
Even assigning a single value does not work:
reg [8:1] char_value;  
always @(reset) 
begin
    char_value = "A";
    if (char_value == 8'h41)
        // Do stuff!
I want to shift the individual characters on an 8-bit bus to an LCD screen for display.
How can I work with strings in Verilog?
                @Adam12 - Yes, I'm trying to print text on an LCD screen connected to my FPGA development board. Since this wasn't clear to both you and toolic, I'll edit the question to be more specific: I want to assign these 8-bit character values to an output of my module through a shift register.
– Kevin Vermeer
                Jan 29, 2012 at 2:56
                What exactly does not work? Do you get a synthesis error, or is the text simply not shown on the LCD?
– mkrieger1
                Feb 10, 2017 at 14:58
                To be clear. The verilog compiler will translate "A" to 8'h41, "AB" to 16'h4142, "ABC" to 24'h434241. Do not make it more complicated on yourselves by trying to think that the FPGA has to "support" this some how. All that happens is the compiler converts it from a nice human readable format into a number.
– Stephen
                Sep 13, 2012 at 11:01
                Yes string values are just constants. Although synthesis tool may or may not allow registers to have non-zero initialisation/reset values depending on the technology used. Recent X/A tools have no problem initialising shift registers from constants straight out of reset/programming.
– shuckc
                Jul 2, 2013 at 16:38
You now have a constant with ASCII values in it that you can index into. 
reg [7:0] data_out;
reg       data_out_valid;
reg [3:0] some_index;
// pushing data onto a bus
data_out       <= foo[some_index];
data_out_valid <= 1'd1;
some_index     <= some_index + 4'd1;
With appropriate index checking and control that should work.
if (BIWEn==1'b1 ||BIREn==1'b1)
    begin:START_STATE_WRITE
        psW=idleW;  //psW is Present State Write
        string_value1= "IDLE";
![test bench] (c:\pictures)
                For simulation, you can use string or $display. But if you are designing some code for FPGA. I think currently the synthesis tool doesn't support string type. From Xilinx they even doesn't support systemverilog now.
– Enze Chi
                Feb 8, 2012 at 10:07
SystemVerilog should support string assignment as mentioned in spec:
For example, to store the 12-character string "Hello world\n" requires a variable 8x12, or 96 bits wide. 
     bit [8*12:1] stringvar = "Hello world\n";
Not sure if the old verilog supports it or not.
                This answer is completely and utterly incorrect. Verilog does support character constants, and there is certainly nothing preventing a user from assigning hexadecimal values to registers!
– user149341
                Mar 19, 2018 at 1:52
        
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