In this post
, we have introduced the conditional statement. The IF-THEN-ELSE is a VHDL statement that allows implementing a choice between different options. When the number of options greater than two we can use the VHDL “ELSIF” clause. In case of multiple options, VHDL provides a more powerful statement both in the concurrent and sequential version:
As clear from the RTL viewer in Figure2, the VHDL code of the 4-way mux is translated in two different VHDL-RTL implementations. In Figure2 on the left is reported the RTL view of the 4-way mux implemented using the IF-THEN-ELSIF VHDL coding style. A set of comparators are used to select the cascaded 2-way mux as described in the VHDL code. On the right is reported the straight forward 4-way mux implementation as described by the CASE-WHEN VHDL coding style.
Figure 2 – RTL viewer 4-way MUX with different VHDL coding approach
Figure 3 – Technology viewer 4-way MUX with different VHDL coding approach
Different RTL views can be translated in the same hardware structure!
wait, wait… different RTL implementation can be translated in the same hardware circuit?
Yes!
As I always say to every guy that contact me,
you must think hardware!
Think about it: even if you are writing a VHDL code using IF-THEN-ELSIF statement, the final output comes from a 4-way mux. The logic synthesizer does its work simplifying the Boolean equations that come from your VHDL-RTL coding giving as result the 4-way mux we want to implement.
Conclusion
Every time we write a VHDL code to implement some hardware circuit, we need to pay attention to which VHDL instruction or construct is better to use.
As a rule of thumb, the selection of the RTL architecture is should be guided by the similarity of VHDL-RTL code to the final hardware.
A very good practice is also to verify the RTL viewer implementation and eventually, the final technology implementation both on the output reports and the technology viewer.
Reference
[1] RTL HARDWARE DESIGN USING VHDL Coding for Efficiency, Portability, and Scalability
[2] VHDL Programming by Example 4th Ed Douglas – Perry
Good afternoon:
It is a very interesting paper, but The example commented corresponds to a Combinational logic, but you only analyzed two examples using the process command (sequential). So, I added another example using with-select-when command:
architecture rtl of mux4_case is
begin
with s select
m <=a when "00",
b when "01",
b when "10",
d when others;
end rtl;
I tried the three options in VIVADO and got the same implemented results but with LUT's, (different to the ones shown in your article), anyway confirming your statement.
