rob.myers (Member) asked a question.
[VRFC 10-529] concurrent assignment to a non-net P is not permitted
I have tried to change my declaration of 'P' from a reg to a wire, but the error does go away. It went away when i removed my 'P' from out of the declaration but when I ran the simulation, i didnt get an output. Below is a piece of my code pertaining to the error messages to include the declaration area:
module Array_4x4_Multiplier(P, A, B);
output reg [7:0] P;
input [3:0] A, B;
wire [6:1] S;
wire [11:1] C;
wire [15:0] W;
and A1(P[0], A[0], B[0]);
The continuous assignment you are using is only allowed on "net" types.
So, whenever you declare P as wire the error will not be there.
For this multiplier design (which is purely combinational), the output should be of net datatype as you don't need to retain the value on output until another value is placed on it (which is the case for sequential circuits). You just want output to be continuously driven by the logic which you are implementing. So just declare it as
output [7:0] P;
Another thing to note is when instantiating verilog primitives, the portmapped signals which are used should be of net datatype. I tried this test case with above declaration and able to simulate it properly with expected output P[0] from AND gate.
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