All possible choices must be included, unless the others clause is used as the last choice:

case SEL is
  when "01" =>   Z <= A;
  when "10" =>   Z <= B;
  when others => Z <= 'X';
end case;
The CASE statement is generally synthesisable.
With repeated assignments to a target signal, it willsynthesise to a
large multiplexer with logic on the select inputs to evaluate the
conditions for the different choices in the case statement branches. No
"priority" will be inferred from the order of the branches
With multiple targets and embedded if statements, the case
statement may be used to synthesise a general mapping function, e.g.
next state and output generation for a finite state machine. For
example:

case READ_CPU_STATE is
  when WAITING =>
    if CPU_DATA_VALID = '1' then
      CPU_DATA_READ  <= '1';
      READ_CPU_STATE <= DATA1;
    end if;
  when DATA1 =>
    -- etc.
end case;
In VHDL-93, the casestatement may have an optional label:
label: case expression is
... etc.