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An error happend when I run make image . And I located at one sentence. It's because of float add and float multiply. Here is the detail of error.

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
ERROR: [DRC INBB-3] Black Box Instances: Cell 'a0/action_w/hls_action_0/grp_process_action_fu_141/grp_CONVOLUTION_LAYER_SW_fu_1074/hls_action_fadd_3dEe_U2/hls_action_ap_fadd_6_full_dsp_32_u' of type 'hls_action_ap_fadd_6_full_dsp_32' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.
ERROR: [DRC INBB-3] Black Box Instances: Cell 'a0/action_w/hls_action_0/grp_process_action_fu_141/grp_CONVOLUTION_LAYER_SW_fu_1074/hls_action_fmul_3eOg_U3/hls_action_ap_fmul_3_max_dsp_32_u' of type 'hls_action_ap_fmul_3_max_dsp_32' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.
INFO: [Project 1-461] DRC finished with 2 Errors
It seems that the IP you are calling is not found in Xilinx library.

  • Can you confirm that during the make image flow, you have the 3 lines I have highlighted below with >> <<?
  • Are you using the latest master branch of the snap git?
  • Which Vivado release are you working with?
  • Are you trying to build an image with make image using the HLS_decimal_mult action or are you using your own action code? If you could first try with the HLS_decimal_mult action, this would validate the entire process first.
  • (extract of the make image flow)

    [CREATE SNAP IPs.....] done  10:11:55 Mon Sep 16 2019                                                         
    [CREATE HLS IPs......] start 10:12:04 Mon Sep 16 2019                                                         
                            >>sourcing hls_action_ap_fmul_3_max_dsp_32_ip.tcl<<                                      
                            >>generating HLS IP hls_action_ap_fmul_3_max_dsp_32<<                                     
    [CREATE HLS IPs......] done  10:12:21 Mon Sep 16 2019                                                         
    [CREATE_FRAMEWORK....] start 10:12:30 Mon Sep 16 2019                                                         
                            setting up project settings                                                           
                            importing design files                                                                
                            importing IP    
                            adding SNAP IP fifo_513x512                                                           
                            adding SNAP IP fifo_10x512                                                            
                            adding SNAP IP fifo_8x512                                                             
                            adding SNAP IP fifo_4x512                                                             
                            >>adding HLS Action IP hls_action_ap_fmul_3_max_dsp_32<<                                  
                            importing CAPI BSP (xcix)                                                             
                            importing XDCs                                                                                
    

    FYI as a test to confirm the entire flow on this specific point, I have just reran successfully the entire make image process with the HLS_decimal_mult action and with the latest snap release using Vivado 2018.2.